1. Field of the Invention
The present invention relates to a wiring substrate for mounting semiconductors, which is capable of mounting various types of devices at high density and high accuracy, particularly, further obtaining a package and a module having a high rate and excellent reliability, a method of manufacturing the same, and a semiconductor package using the wiring substrate.
2. Description of the Related Art
In recent years, in line with high integration, high speed and multi-functioning of semiconductor devices, the number of terminals has been increased, and the distance between pitches has been narrowed. In a wiring substrate for mounting semiconductors, which mounts these semiconductor devices, such a wiring substrate that is capable of mounting semiconductor devices at higher density and higher accuracy than ever before and is more excellent in reliability than ever before has been requested. As examples of a wiring substrate for mounting semiconductors that have been publicly known at present, there are listed a built-up substrate (For example, Japanese Published Unexamined Patent Application No. 2001-284783) in which high-density wiring layers are formed on a core printed circuit board by a successively-laminating method, and a collectively-laminated substrate (For example, Japanese Published Unexamined Patent Application No. 2003-347738) which is composed by collectively laminating resin sheets in which a wiring layer and vias are formed.
FIG. 1 is a sectional view showing a built-up substrate. As depicted in FIG. 1, a multi-layered wiring structure in an insulation layer in a base core substrate 103. Conductor wirings 102, one of which is formed on the upper surface of the base core substrate 103 and the other of which is formed on the lower surface thereof, are connected by a through-hole 101 passing through the insulation layer. On both the upper and lower surfaces of the base core substrate 103, inter-layer insulation films 105 are formed, and conductor wirings 106 are formed on the respective inter-layer insulation films 105. Further, a solder-resist layer 107 is formed on the inter-layer insulation film 105 so as to cover up a part of the conductor wiring 106. A via 104 is formed in the inter-layer insulation film 105 in order to electrically connect the conductor wirings 102 and the conductor wiring 106.
Additionally, if a further multi-layer is required, a multi-layered wiring structure can be formed by repeating a step for forming the inter-layer insulation film 105 and a step for forming the conductor wiring 106 one after another.
On the other hand, FIG. 2A through FIG. 2C are sectional views showing, in the order of step, one example of a method of manufacturing a collectively-laminated substrate. In the collectively-laminated substrate according to a conventional art, as depicted in FIG. 2A, a conductor wiring 112 is formed on a resin sheet 111, and a via 113 connected to the conductor wiring 112 is provided in the resin sheet 111. As depicted in FIG. 2B and FIG. 2C, a collectively laminated substrate 114 is formed, by providing a plurality of such resin sheets 111 and collectively laminating the same.
Still, in the built-up substrate and collectively laminated substrate according to the prior arts, such a structure is employed, in which a conductor wiring is formed on an insulation film, and electrode pads for mounting semiconductors are also formed on the insulation film. In recent years, in line with advancement of high density and minute wiring in the wiring substrates, the method for forming conductor wiring has been changed from a method (subtractive method) for etching a copper foil to a method (additive method) in which a resist layer is patterned with electrodes provided, and an electrolytically plated layer is precipitated and laminated.
However, there is a shortcoming in that electrode pads formed by the additive method are uneven in the height thereof, the shape of the upper surface of electrode pads is not flat but is made convex, wherein it becomes difficult to mount semiconductor devices having a large number of pins and narrow pitches. In addition, although there are generally many cases where a solder resist layer 107 is formed on the electrode pads, it becomes remarkably difficult to make the film thickness of the solder resist layer minute and the opening diameter highly accurate since the heights of the electrode pads have a large imbalance. Further, in line with making the electrode pads minute, the contacting area between the electrode pads and insulation films is lowered, a cohesion force between the electrode pads and insulation films is lowered, and in particular, there causes a problem, by which the electrode pads are stripped from the insulation films in the step of mounting semiconductor devices under high-temperature processing to which lead-free solder is applied.
In order to solve various problems described above, the present applicant proposed a method for forming a wiring structure and electrode pads to mount semiconductor devices thereon on a support body made of a metallic plate and having excellent flatness, and for mounting semiconductor devices on the electrode pads (Japanese Published Unexamined Patent Application No. 2002-83893).
However, in order to mount semiconductor devices at high density in line with remarkable advancement of high performance and multi-functioning in recent mobile apparatuses, the demand for mounting semiconductor devices on both of the front surface and the rear surface of a wiring substrate has been increased. Actually, however, although a conventional wiring substrate described in Japanese Published Unexamined Patent Application No. 2002-83893 described above is sufficient in a case where semiconductor devices are mounted on one surface, it is still difficult to mount semiconductor devices at high density in a case of mounting the same on both surfaces.
Further, for achievement of high reliability of a semiconductor package, it is highly recommended that a film having a lower thermal expansion ratio and a lower resiliency ratio is applied to a part of inter-layer insulation films that compose a wiring substrate for mounting semiconductors. However, with a conventional wiring substrate described above, there is a problem in that a lowering in structural reliability results from if insulation films having different physical properties are applied.